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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Full 16-Bit Performance 1 LSB Max INL and DNL Maximum Output Voltage Range of 10V Settling Time of 10s max at 16 bits Clear Function to 0 V Asynchronous Update of Outputs (LDAC pin) Power On Reset Serial Data Output for Daisy Chaining Data Readback Facility Temperature Range -40 C to +125 C APPLICATIONS Industrial Automation Automatic Test Equipment Process Control Data Acquisition Systems General Purpose Instrumentation
12 V/15 V, Serial Input Voltage Output, 16 Bit DAC AD5570
FUNCTIONAL BLOCK DIAGRAM
VSS VDD DGND
AD5570
2*RDAC
POWER ON RESET
REFGND
+
R R R
16 - BIT DAC
+
VOUT AGND AGNDS
REFIN
+
-
R
DAC REGISTER
LDAC
SHIFT REGISTER
POWER-DOWN CONTROL LOGIC
PD
SDIN
SCLK
SYNC
SDO
CLR
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD5570 is a single 16-bit serial input, voltage output DAC that operates from supply voltages of 12 V up to 15 V. INL and DNL are accurate to 1LSB (max) over the full temperature range of -40C to +125C. The AD5570 utilizes a versatile three-wire interface that is compatible with SPI TM, QSPITM, MICROWIRE TM and DSP interface standards. Data is presented to the part in the format of a sixteen bit serial word. Serial Data is available on the SDO pin for daisy chaining purposes. Data Readback allows the user to read the contents of the DAC register via the SDO pin. During power-up and power-down sequences (when the supply voltages are changing), VOUT is clamped to 0 V via a low impedence path. LDAC may be used to update the output of the DAC. A Power Down (PD) pin allows the DAC to be put into a low power state, and a CLR pin allows the output to be cleared to 0 V. The AD5570 is available in a 16-pin SSOP package.
1. Buffered Voltage Output up to 10V. 2. 1 LSB max INL and DNL 3. Wide Temperature Range of -40 C to +125 C.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
AD5570-SPECIFICATIONS1
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Bipolar Zero Error Gain Temperature Coefficient 2 REFERENCE INPUT Reference Input Range Input Current O/P CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse DAC Output Impedance 2 Digital Feedthrough Power Supply Rejection Ratio LOGIC INPUTS Input Current VINH, Input High Voltage VINL, Input Low Voltage CIN, Input Capacitance2 Hystersis Voltage LOGIC OUTPUTS VOL, Output Low Voltage Floating-State Leakage Current Floating-State O/P Capacitance POWER VDD/VSS REQUIREMENTS 11.4 16.5 5 5 20 1 100 A Grade 16 1 1 16 16 16 1 3 5 1
PRELIMINARY TECHNICAL DATA
(VDD = +11.4 V to +16.5 V ; VSS = -11.4 V to -16.5 V; VREF = 5V; GND = 0 V; RL = 5 k and CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted)
Units Test Conditions/Comments
LSB LSB LSB LSB LSB ppm ppm
Bits max max Guaranteed Monotonic Over Temperature max max max FSR/C typ FSR/C max
V max A max V max V min s max V/s typ nV-s typ max nV-s typ dB min A max V min V max pF max V typ V max A max pF typ V min V max mA max mA max A max LSB/V max mW typ ISINK = 1 mA
VDD - 1.4 V VSS + 1.4 V 10 10 12 0.3 5 75 1 2.0 0.8 44 0.15 0.4 1 3
At 16 bits to 0.5 LSB Measured from 10% to 90% 1 LSB Change around the Major Carry
IDD ISS Power-down Current Power Supply Sensitivity 3 Power Dissipation
V OUT Unloaded
V OUT Unloaded
NOTES 1 Temperature range: -40C to +125C. 2 Guaranteed by design. 3 Sensitivity of Gain Error and Bipolar Zero Error to V DD , V SS variations Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD5570
(VDD = +12 V 10%, VSS = -12 V 10% or VDD = +15 V 10%, VSS =-15 V 10%; VREF = 5V; GND = 0 V; RL = 5 k and CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted)
Parameter f MAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 t 12 t 13 t 14
1 2
STANDALONE TIMING CHARACTERISTICS1,2
Limit at TMIN, TMAX 8 125 50 50 40 30 10 40 40 0 40 0 20 0 40 Units MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description SCLK Frequency SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Min SYNC high time SYNC Rising Edge to LDAC Falling Edge LDAC Pulsewidth LDAC Rising Edge to SYNC Falling Edge SCLK Falling Edge to LDAC Rising Edge SCLK Falling Edge to LDAC Falling Edge CLR pulse width
Guaranteed by design and characterization. Not production tested. All input signals are measured with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL +V IH )/2. Specifications subject to change without notice.
t1 SCLK t2 t8 SYNC t6 t5 SDIN DB15 DB0 DB0 t9 LDAC1 t13 LDAC2 t10 t4 t3 t7
t11 t12
CLR Notes 1. ASYNCHRONOUS LDAC UPDATE MODE 2. SYNCHRONOUS LDAC UPDATE MODE
t14
Figure 1. Serial Interface Timing Diagram
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AD5570
PRELIMINARY TECHNICAL DATA
(VDD = +12 V 10%, VSS = -12 V 10% or VDD = +15 V 10%, VSS =-15 V 10%; VREF = 5V; GND = 0 V; RL = 5 k and CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted)
Parameter f MAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 t 15
1 2
DAISY CHAINING AND READBACK TIMING CHARACTERISTICS1,2,3
Limit at TMIN, TMAX 2 500 200 200 40 30 10 40 40 0 20 0 40 Units MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Description
SCLK Frequency SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Min SYNC high time SYNC Rising Edge to LDAC Falling Edge LDAC Pulsewidth LDAC Rising Edge to SYNC Falling Edge Data delay on SDO
Guaranteed by design and characterization. Not production tested. All input signals are measured with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL +V IH)/2. 3 SDO; R PULLUP = 5k, C L = 15pF. Specifications subject to change without notice.
t1 SCLK t8 SYNC t10 t9 LDAC2 t5 SDIN DB15 (N) t6 t4 t3 t2 t7 t11
LDAC1
DB0 (N)
DB15 (N+1)
DB0 (N+1) t15
SDO
DB15(N)
DB0(N)
DB15 (N+1)
Notes 1. ASYNCHRONOUS LDAC UPDATE MODE 2. SYNCHRONOUS LDAC UPDATE MODE
Figure 2. Daisy Chaining Timing Diagram
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PRELIMINARY TECHNICAL DATA AD5570
t1 SCLK t2 t8 SYNC t6 t5 DIN DB15(N) DB0(N)
DB15 (N+1)
t3 t7
t4
DB0 (N+1)
t10 LDAC t9 t11
SDO
DB15(N)
DB14(N)
DB0(N)
Figure 3. Readback Timing Diagram
ABSOLUTE MAXIMUM RATINGS1
(T A = +25C unless otherwise noted)
VDD to AGND, DGND .......................... -0.3 V, +17 V V SS to AGND, DGND.............................+0.3 V, -17 V AGND to DGND ....................-0.3 V to VDD to +0.3 V REFOUT to AGND ...................................0 V to VDD REFIN to AGND ....................-0.3 V to VDD to +0.3 V Digital Inputs to DGND.................-0.3V to VDD +0.3 V SDO to DGND ................................... -0.3V to +6.5 V Operating Temperature Range ............. -40C to +125C Storage Temperature Range ................ -65C to +150C Maximum Junction Temperature, (TJ max) .........+150C 16-Lead SSOP Package Power Dissipation ........................... (TJ max - TA)/JA JA Thermal Impedance ............................... 139 C/W
Lead Temperature (Soldering 10s) ....................... 300C IR Reflow, Peak Temperature ............................+220 C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD5570YRS
Temperature Range -40 C to +125 C
Description Shrink SO package
Package RS-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5570 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.
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AD5570
PRELIMINARY TECHNICAL DATA
PIN CONFIGURATION 16 Lead SSOP RS-16
VSS VDD CLR LDAC SYNC SCLK DIN SDO
1 2 3 4 5 6 7 8
16 15
REFGND REFIN REFGND VOUT AGNDS AGND PD DGND
AD5570
TOP VIEW
(Not to Scale)
14 13 12 11 10 9
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4
Mnemonic VSS VDD CLR LDAC SYNC
Description Negative analog Supply Voltage, -12 V 5% to -15 V 10% for specified performance. Positive analog Supply Voltage, +12 V 5% to +15 V 10% for specified performance. Level Sensitive, active low input. A falling edge of CLR resets VOUT to AGND. The contents of the registers are untouched. Active low control input that transfers the contents of the input register to the DAC register. LDAC may be tied permanently low enabling the outputs to be updated on the rising edge of SYNC. Active Low Control input. This is the frame synchronisation signal for the data. When SYNC goes low, it powers on the SCLK and SDIN buffers and enables the input shift register. Data is transfered in on the falling edges of the following 16 clocks. Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can be transfered at rates up to 8 MHz. Serial Data input. This device has a 16-bit register. Data is clocked into the register on the falling edge of the serial clock input. Serial Data Output that can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. This is an open-drain output; it should be pulled high with an external pull-up resistor. Digital Ground. Ground reference for all digital circuitry. Active low control input that allows the DAC to be put in a powerdown state. Analog Ground. Ground reference for all analog circuitry. Analog Ground Sense. This is normally tied to AGND. Analog output Voltage. This pin should be tied to 0 V. Voltage Reference Input. It is internally buffered before being applied to the DAC. For bipolar 10 V output range, REFIN is 5 V. This pin should be tied to 0 V.
5
6 7 8
SCLK SDIN SDO
9 10 11 12 13 14 15 16
DGND PD AGND AGNDS VOUT REFGND REFIN REFGND
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PRELIMINARY TECHNICAL DATA AD5570
TERMINOLOGY Relative Accuracy Full Scale Error
Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function.
Monotonicity
This is the error in the DAC output voltage when all 1s are loaded to the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF - 1 LSB.
Bipolar Zero Error
A DAC is monotonic if the ouput either increases or remains constant for increasing digital inputs. The AD5570 is monotonic over its full operating temperature range.
Differential Non-Linearity
The deviation of the analog input from the ideal half-scale output of 0.0000V when the inputs are loaded with 8000H is called Bipolar Zero Error.
Output Voltage Settling Time
Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
Gain Error
This is the amout of time it takes for the output to settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
Gain Error is the difference between the actual ans ideal analog output range, expressed as a percent of the fullscale range. It is the deviation in slope of the DAC transfer characteristic from ideal.
Gain Error Temperature Coefficient
This is the amount of charge injected put when the input code in the DAC state. It is specified as the area of the measured when the digital input code the major carry transition.
Digital Feedthrough
into the analog outregister changes glitch in nV-s and is changes by 1 LSB at
This is a measure of the change in gain error with changes in temperature. It is expressed in ppm/ C.
Zero Scale Error
Zero Scale Error is the error in the DAC output voltage when all 0s are loaded into the DAC latch. Ideally, the output voltage, with all 0s in the DAC latch, should be equal to -2 VREF. Zero-scale error is mainly due to offsets in the output amplifier.
Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. SYNC is held high, while the CLK and SDIN signals are toggled. It is specified in nV-s and is measured with a full scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
Power Supply Rejection Ratio
This specification indicates how the output of the DAC is affected by changes in the power supply voltage.
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AD5570
PRELIMINARY TECHNICAL DATA
tive and negative reference for the DAC core. The positive reference is given by + VREF = 2 x VREFIN while the negative reference to the DAC core is - VREF = -2 x VREFIN The reference buffers are shown in Figure 5 below.
SERIAL INTERFACE
GENERAL DESCRIPTION
The AD5570 is a single 16-bit, serial input, voltage output DAC. It operates from supply voltages of 12 V to 15 V, and has a buffered voltage output of up to 10 V. Data is written to the AD5570 in a 16-bit word format, via a 3-wire serial interface. It also has an SDO pin which is available for daisy-chaining or readback. The AD5570 incorporates a power-on-reset circuit which ensures that the DAC output powers up to 0V. The device also has a power-down pin which reduces the current consumption to 20 A.
DAC Architecture
The AD5570 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE and DSP interface standards.
Input Shift Register
The DAC architecture of the AD5570 consists of a 16-bit current-mode segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 4. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGND or IOUT. The remaining 12 bits of the data word drive switches S0 to S11 of the 12-bit R-2R ladder network.
R Vref 2R 2R 2R R R
2R
2R
2R
2R
R/8 E15 E14 E1 S11 S10 S0 Vout To OP-AMP AGND 4 MSBs DECODED INTO 15 EQUAL SEGMENTS 12 BIT R-2R LADDER
Figure 4. DAC Ladder Structure
Reference Buffers
The AD5570 operates with an external reference. The reference input (REFIN) has an input range of up to 5V. This input voltage is then used to provide a buffered posi-
The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 1. Upon power-up, the input shift register and DAC register are loaded with midscale (8000H). The DAC coding is straight binary; all 0s produces an output of -2 VREF; all 1s produces an output of +2 VREF - 1 LSB. The SYNC input is a level-triggered input that acts as a frame synchronisation signal and chip enable. SYNC must frame the serial word being loaded into the device. Data can only be transfered into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data on SDIN will be shifted into the device's input shift register on the falling edges of SCLK. SYNC may be taken high after the falling edge of the sixteenth SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. After the end of the serial data transfer, data will automatically be transferred from the input shift register to the input register of the DAC. When data has been transfered into the input register of the DAC, the DAC register and DAC output can be updated by taking LDAC low while SYNC is high.
Figure 5. The voltage at VREFIN provides a buffered positive and negaitve reference for the DAC core
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PRELIMINARY TECHNICAL DATA AD5570
Load DAC Input (LDAC)
When data has been transfered into the input register of the DAC, there are two ways in which the corresponding DAC register and DAC output can be updated. Depending on the status of both SYNC and LDAC, one of two update modes is selected. Synchronous LDAC: Here, LDAC is low while data is being clocked into the input shift register. The DAC output is updated when SYNC is taken high. The update here occurs on the rising edge of SYNC. Asychronous LDAC: In this case, LDAC is high while data is being clocked in. The DAC output is updated by taking LDAC low any time after SYNC has been taken high. The update now occurs on the falling edge of LDAC. Figure 6 shows a simplified block diagram of the input loading circuitry.
OUTPUT I/V AMPLIFIER VREF I N 16-BIT DAC VOUT
The outputs of all the DACs in the system can be updated simultaneously using the LDAC signal.
U 68HC11* MOSI SCK PC7 PC6 MISO SDIN SCLK SYNC LDAC SDO R SDIN AD5570* SCLK SYNC LDAC SDO R VDD AD5570*
LDAC SYNC
DAC REGISTER
SDIN AD5570*
SDIN
INPUT SHIFT REGISTER
SDO
SCLK SYNC LDAC
Figure 6. Simplified Serial Interface
Daisy Chaining
SDO R *ADDITIONAL PINS OMITTED FOR CLARITY
This mode of operation is designed for multi-DAC systems where several AD5570s may be connected in cascade as shown in figure 7. This is done by connecting the control inputs in parallel, and then daisy-chaining the SDIN and SDO I/O's of each device. Also, an external pull-up resistor of ~5 k on SDO is required when using the part in daisy-chain mode. As before, when SYNC goes low, serial data on SDIN will be shifted into the input shift register on the rising edge of SCLK. If more than 16 clock pulses are applied, the data ripples out of the shift resister and appears on the SDO line. By connecting this line to the SDIN input on the next AD5570 in the chain, a multi-DAC interface may be constructed. One data transfer cycle of sixteen SCLK pulses is required for each DAC in the system. Therefore, the total number of clock cycles must equal 16N where N is the total number of devices in the chain. The first data transfer cycle written into the chain will appear at the last DAC in the system on the final data transfer cycle. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data being clocked into the device. A continuous SCLK source may be used if it can be arranged that SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later.
Figure 7. Daisy-chaining using the AD5570
Readback
The AD5570 allows the data contained in the DAC resigter to be readback if required. As with daisy-chaining, an external pull-up resistor of ~5 K on SDO is required. The data in the DAC register is available on SDO on the falling edges of SCLK when SYNC is low. On the 16th SCLK edge, SDO is updated to repeat SDIN with a delay of 16 clock cycles. In order to readback the contents of the DAC register without writing to the part, SYNC should be taken low while LDAC is held high. Daisy-chaining readback is also possible, since SDO containing the DAC data passes through the DAC chain with the appropriate latency.
Power-on Reset
The AD5570 contains a power-on-Reset circuit that controls the output during power-up and power-down. This is useful in applications where the known state of the output of the DAC during power up is important. On power up and powerdown, the output of the DAC, VOUT, is held at AGND.
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AD5570
TRANSFER FUNCTION
PRELIMINARY TECHNICAL DATA
Table 1 below shows the ideal input code to output voltage relationship for the AD5570.
Binary Code Table
Digital Input MSB 1111 1000 1000 0111 0000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000
LSB 1111 0001 0000 1111 0000
Analog Output V OUT +2VREF x (32,767/32,768) +2VREF x (1/32,768) 0V -2VREF x (1/32,768) -2V REF
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PRELIMINARY TECHNICAL DATA AD5570
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6.50 6.20 5.90
16
9
8.20 7.80 7.40
1 8
5.60 5.30 5.00
2.00 MAX
1.85 1.75 1.65
0.25 0.09 88 48 08 0.95 0.75 0.55
0.05 MIN 0.65 BSC
0.38 0.22
SEATING PLANE
COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-150AC
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